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? integrated circuits group lh 28 f 008 sc r -l 85 fla sh me mor y 8 m ( 1 m 8 ) (model no.: lh f 08 ch 2 ) spec no.: el 10 40 2 9 b issue date: feb ru ar y 1 , 19 99 p roduc t s pecific a tions
sharp lhf08ch2 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (z), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics l instrumentation and measuring equipment .machine tools @audiovisual equipment *home appliance l communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands hiah reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *control and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers atraffic control systems @gas leak detectors and automatic cutoff devices 6escue and security equipment @other safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. *aerospace equipment *communications equipment for trunk lines *control equipment for the nuclear power industry l medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. *please direct all queries regarding the products covered herein to a sales representative of the company. rev.l.l
sharp lhfosch2 1 contents page page i .o introduction ................................................... 3 1 .l new features ...................................................... 3 1.2 product overview.. .............................................. 3 2.0 principles of operation.. ........................... 7 2.1 data protection ................................................... 7 3.0 bus operation ................................................. 8 3.1 read ................................................................... 8 3.2 output disable .................................................... 8 3.3 standby.. ............................................................. 8 3.4 deep power-down .............................................. 8 3.5 read identifier codes operation.. ....................... 9 3.6 write .................................................................... 9 5.0 design considerations ............................. .2? 5.1 three-line output control ................................ .2? 5.2 ry/by# and block erase, byte write and lock-bit configuration polling ........................................... 25 5.3 power supply decoupling.. ................................ 24 5.4 v,, trace on printed circuit boards.. ............... .2f 5.5 v,,, v,,, rp# transitions ................................. 24 5.6 power-up/down protection ................................ 24 5.7 power dissipation ............................................. .24 1.0 command definitions. ................................... 9 4.1 read array command.. ..................................... 12 4.2 read identifier codes command ...................... 12 4.3 read status register command.. ..................... 12 4.4 clear status register command.. ..................... 12 4.5 block erase command.. .................................... 12 4.6 byte write command ........................................ 13 4.7 block erase suspend command.. ..................... 13 4.8 byte write suspend command.. ....................... 14 4.9 set block and master lock-bit commands.. ..... 14 4.10 clear block lock-bits command.. ................... 15 6.0 electrical specifications.. ..................... .2e 6.1 absolute maximum ratings ............................... 25 6.2 operating conditions ......................................... 25 6.2.1 capacitance ................................................. 25 6.2.2 ac input/output test conditions.. ............... .2e 6.2.3 dc characteristics ........................................ 27 6.2.4 ac characteristics - read-only operations .2e 6.2.5 ac characteristics - write operations.. ....... .34 6.2.6 alternative ce#-controlled writes.. ............. .3e 6.2.7 reset operations ........................................ .3e 6.2.8 block erase, byte write and lock-bit configuration performance.. ........................ .3e 7.0 additional information ............................ .40 7.1 ordering information .......................................... 40 8.0 package and packing specifications ..4 1 j rev. 1.0
lhf08ch2 2 LH28F008SCR-L85 8-mbit (1 mb x 8) smartvoltage flash memory n smartvoltage technology n enhanced automated suspend options - 2.7v(read-only), 3.3v or 5v vcc - byte write suspend to read - 3.3v, 5v or 12v vpp - block erase suspend to byte write - block erase suspend to read n high-performance read access time - 85ns(5v-c0.25v), 90ns(5vk0.5v), n enhanced data protection features 120ns(3.3v=0.3v), 150ns(2.7v-3.6v) - absolute protection with vpp=gnd - flexible block locking n operating temperature - block erase/byte write lockout - 0c to +7o?c during power transitions n high-density symmetrically-blocked n extended cycling capability architecture - 100,000 block erase cycles - sixteen 64-kbyte erasable blocks - 1.6 million block erase cycles/chip n low power management n industry-standard packaging - deep power-down mode - 40-lead tsop (reverse bend) - automatic power savings mode decreases icc in static mode n etoxtm* nonvolatile flash technology i automated byte write and block erase n cmos process - command user interface (p-type silicon substrate) - status register n not designed or rated as radiation i sram-compatible write interface hardened sharp?s lh28f008scfgl85 flash memory with smartvoltage technology is a high-density, low-cost, nonvolatile, ,ead/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage ind extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F008SCR-L85 offers three levels of protection: absolute protection with v,, at ;nd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the LH28F008SCR-L85 is manufactured on sharp?s 0.38um etoxtm process technology. it come in ndustry-standard package: the 40-lead tsop, ideal for board constrained applications. based on the 28f008sa architecture, the LH28F008SCR-L85 enables quick and easy upgrades for designs demanding the state-of-the-art. etox is a trademark of intel corporation. rev.1.11
sharf=@ lhf08ch2 3 1 introduction this datasheet contains lh28f008scrl85 specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. lh28f008scrl85 flash memory documentation also includes application notes and design tools which are referenced in section 7. 1.1 new features the lh28f008scrl85 smartvoltage flash memory maintains backwards-compatibility with sharp?s ?8f008sa. key enhancements over the 28f008sa nclude: *smartvoltage technology *enhanced suspend capabilities *in-system block locking 30th devices share a compatible pinout, status ,egister, and software command set. these similarities enable a clean upgrade from the !8f008sa to LH28F008SCR-L85. when upgrading, t is important to note the following differences: *because of new feature support, the two devices have different device codes. this allows for software optimization. l vpplk has been lowered from 69 to 1.5v to support 3.3v and 5v block erase, byte write, and lock-bit configuration operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smartvoltage technology, allow v,, connection to 3.3v or 5v. i .2 product overview ?he LH28F008SCR-L85 is a high-performance 8-mbit ;martvoltage flash memory organized as 1 mbyte of i bits. the 1 mbyte of data is arranged in sixteen ickbyte blocks which are individually erasable, jckable, and unlockable in-system. the memory lap is shown in figure 3. smartvoltage technology provides a choice of v,, and v,, combinations, as shown in table 1, to meet system performance and power expectations. 2.7v vc, consumes approximately one-fifth the power of 5v voo. but, 5v voo provides the highest read performance. v,, at 3.3v and 5v eliminates the need for a separate 12v converter, while v,,=12v maximizes block erase and byte write performance in addition to flexible erase and program voltages the dedicated v,, p in ives complete data protectior g when v,, i vpplk. table 1. v,, and vp, voltage combinations > note: 1. block erase, byte write and lock-bit configuratior operations with vcoc3.ov are not supported. internal vcc and vp, detection circuit4 automatically configures the device for optimizec read and write operations. a command user interface (cui) serves as the interface between the system processor and interna operation of the device. a valid command sequence written to the cui initiates device automation. ar internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuratior operations. a block erase operation erases one of the device?s 64-kbyte blocks typically within 0.3 s (5v v,,, 12v v,,) independent of other blocks. each block can be independently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 6 us (5v voo, 12v vp,). byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.2
sham= lhf08ch2 4 individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. lock-bit configuration operations (set block lock-bit, set master lock-bit, and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, byte write, or lock-bit configuration operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is oerforming a block erase, byte write, or lock-bit zonfiguration. ry/by#-high indicates that the wsm is ?eady for a new command, block erase is suspended [and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. the access time is 85 ns (t,.,,,*,,) over the commercia temperature range (0c to +70x) and vco supply voltage range of 4.75v-5.25v. at lower vco voltages, the access times are 90 ns (4.5v-5sv), 120 ns (3.ov-3.6v) and 150 ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i,,, current is 1 ma at 5v vcc. when ce# and rp# pins are at voc, the icc cmos standby mode is enabled. when the rp# pin is al gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 40-lead tsop (thin small outline package, 1.2 mm thick, reverse bend). pinout is shown in figure 2. rev.1.0
sharp lhf08ch2 5 r . . 3 + * . . . . . . . . . . fff ce# \ve# (x3 rpb? figure 1. block diagram nc nc we# oe# ry/by# dq7 dq6 dq5 dq4 vcc gnd gnd dq3 dq2 dql dqo 2 a2 a3 49 a16 a17 al6 a15 a14 a13 a12 ce# vcc vpp rp# 41 40 a9 a6 a7 a6 a5 a4 40-lead tsop standard pinout 1 omm x 20mm top view figure 2. tsop 40-lead pinout (reverse bend) rev. 1 .ll
sl-iarp r lhf08ch2 6 1 symbol a& 9 dqc-dq, ce# rp# oe# we# ry/by# ?pp ?cc gnd nc type input input/ output input input input input output supply supply supply table 2. pin descriptions name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs: inputs data and commands durino cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. rp# at v,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp#=v,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with vih lhf08ch2 7 2 principles of operation the LH28F008SCR-L85 smartvoltage flash memory includes an on-chip wsm to manage block erase, byte write, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register and identifier codes can be accessed through the cui independent of the v,, voltage. high voltage on v,, enables successful block erasure, byte writing, and lock-bit configuration. all functions associated with altering memory contents-block erase, byte write, lock-bit configuration, status, and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, byte write, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. nterface software that initiates and polls progress of ,lock erase, byte write, and lock-bit configuration can ie stored in any block. this code is copied to and executed from system ram during flash memory jpdates. after successful completion, reads are igain possible via the read array command. block erase suspend allows system software to suspend a ilock erase to read or write data from any other ilock. byte write suspend allows system software to suspend a byte write to read data from any other lash memory array location. 2.? 1 data protection fffff i f0000 effff eoooo dffff do000 cffff coooo bffff boow affff aoodo bffff 9qooo 6ffff kmo 7ffff 70000 bffff 60000 sffff sow0 4ffff 40000 jffff 30000 pffff 2oooo 1 ffff 1oocil offff t 64-kbyte block 1 64-kbyte block 0 00000 ? i i 64-kbyte block 131 64-kbyte block 12 i 64-kbyte block 81 64-kbyte block 7 i 64-kbyte block 61 64-kbyte block 5 64-kbyte block 4 hgure 3. memory map depending on the application, the system designer may choose to make the v,, power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to vpphij2/s. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vp+vpplk, memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v,,. all write functions are disabled when vcc is below the write lockout voltage vlko or when rp# is at v,,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. rev. 1.0
lhfosch2 a 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, or status register independent of the v,, voltage. rp# can be at either v,, or v,,. the first task is to write the appropriate read mode command (read array, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. four control pins dictate the data flow in and out of the component: ce#, oe#, we#, and rp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dqo-dq,) control and when active drives the selected memory data onto the i/o bus. we# must be at v,, and rp# must be at v,, or v,,. figure 15 illustrates a read cycle. 3.2 output disable with oe# at a logic-high level (v,,), the device outputs are disabled. output pins dqc-dq, are 3laced in a high-impedance state. 3.3 standby ze# at a logic-high level (v,,) places the device in standby mode which substantially reduces device lower consumption. dqc-dq, outputs are placed in 3 high-impedance state independent of oe#. if deselected during block erase, byte write, or lock-bit :onfiguration, the device continues functioning, and consuming active power until the operatior completes. 3.4 deep power-down rp# at v,, initiates the deep power-down mode. in read modes, rp#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. rp# must be held low foi a minimum of 100 ns. time tphqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, norma operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, configuration ~;~low~rit~~ll o;botck;;; modes, - ? operation. ry/by# remains low until the resei operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time tphwl is required after rp# goes to logic-high (vi,) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.0
lhf08ch2 9 5 read identifier codes operation re read identifier codes operation outputs the anufacturer code, device code, block lock nfiguration codes for each block, and the master :k configuration code (see figure 4). using the anufacturer and device codes, the system cpu can rtomatically match the device with its proper gorithms. the block lock and master lock nfiguration codes identify locked and unlocked lcks and master lock-bit setting. foo02 1 block 15 lock configuration code foooi foooo reserved for future implementation (blocks 2 through 14) 1ffff 10004 10003 reserved for future implementation 100021 block 1 lock configuration code 1 10001 reserved for 10000 future implementation btock 1 . offff reserved for future implementation 00004 00003 master lock configuration code 00002 block 0 lock configuration code ______---____-----__~-------------~~~~ 00001 device code __-------_--------~--------~~~~~~~~~~ manufacturer code ?igure 4. device identifier code memory map 3.6 write writing commands to the cui enable reading o device data and identifier codes. they also contra inspection and clearing of the status register. wher vpp=vppht/2/3, the cui additionally controls bloc1 erasure, byte write, and lock-bit configuration. the block erase command requires appropriatt command data and an address within the block to bc erased. the byte write command requires the command and address of the location to be written set master and block lock-bit commands require the command and address within the device (maste lock) or block within the device (block lock) to bc locked. the clear block lock-bits command require: the command and address within the device. the cui does not occupy an addressable memog location. it is written when we# and ce# are active the address and data needed to execute a commanc are latched on the rising edge of we# or cef (whichever goes high first). standard microprocessor write timings are used. figures 16 and 17 illustrate we# and ce#-controlled write operations. 4 command definitions when the v,, voltage i v,,,,, read operation: from the status register, identifier codes, or block: are enabled. placing vpphliti3 on v,, enable: successful block erase, byte write and lock-bi configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines the.% commands. rev. 1.0
lhf08ch2 10 table 3. bus operations mode notes rp# ce# oe# we# address vpp dqil, ry/by# read 1,2,3,8 v$h or hh ?il ?il ?i, x x dout x output disable 3 ?1, or x vhh ?il ?i, ?i, x x high z standby deep power-down read identifier codes 3 vih or vhh ?i, x x x x high z x 4 v,, x x x x x high z vnl, 8 vlh or v# ?il ?il ?i, see figure 4 x note 5 ?oh write uotes: 3,6,7,8 v$+ or ?il ?i, ?il x x dln x hh i. refer to dc characteristics. when vpp lhf08ch2 , command table 4. command definitions(g) bus cycles first bus cycle second bus cycle req?d. notes oper(l) 1 add&*) 1 data@) 1 oper(l) 1 addr(*) 1 data(3) read array/reset 1 1 write 1 x 1 ffh 1 read identifier codes 22 1 4 1 write [ x ( 90h i read 1 ia id i read status register 2 clear status register 1 block erase 2 write x 70h read x srd write x 50h 5 write ba 20h write ba doh 40h 1 byte write i 2 1 56 1 write 1 wa 1 or i write i wa i wd /i block erase and byte write co ,.-..a?4 10h 5 write x boh / block eraseand byte write 1 / 5 / write ( x ( doh ( rlc?3?i i icz set block lock-bit 2 7 write ba 60h write ba olh set master lock-bit 2 7 write x 60h write x flh clear block lock-bits 2 8 write x 60h write x doh notes: 1. bus operations are defined in table 3. 2. x=any valid address within the device. ia=ldentifier code address: see figure 4. ba=address within the block being erased or locked. wa=address of memory location to be written. 3. srd=data read from status register. see table 7 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see section 4.2 for read identifier code data. 5. if the block is locked, rp# must be at v,, to enable block erase or byte write operations. attempts to issue a block erase or byte write to a locked block while rp# is vi,. 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. if the master lock-bit is set, rp# must be at v,, to set a block lock-bit. rp# must be at v,, to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is vi,. 8. if the master lock-bit is set, rp# must be at v,, to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is v,,. 9. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1 .o
lhf08ch2 12 4.1 read array command upon initial device power-up and after exit from deep oower-down mode, the device defaults to read array node. this operation is also initiated by writing the read array command. the device remains enabled ?or reads until another command is written. once the nternal wsm has started a block erase, byte write or ock-bit configuration, the device will not recognize :he read array command until the wsm completes ts operation unless the wsm is suspended via an erase suspend or byte write suspend command. the read array command functions independently of :he v,, voltage and rp# can be v,, or v,,. 4.2 read identifier codes command the identifier code operation is initiated by writing the qead identifier codes command. following the :ommand write, read cycles from addresses shown in ?igure 4 retrieve the manufacturer, device, block lock :onfiguration and master lock configuration codes see table 5 for identifier code values). to terminate he operation, write another valid command. like the ?ead array command, the read identifier codes :ommand functions independently of the v,, voltage %nd rp# can be v,, or v,,. following the read dentifier codes command, the following information :an be read: table 5. ideni code manufacture code device code block lock configuration *block is unlocked *block is locked *reserved for future use master lock configuration @device is unlocked *device is locked *reserved for future use 30te: ier codes tifi 1 . x selects the specific block lock configuration code to be read. see figure 4 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when i block erase, byte write, or lock-bit configuration is complete and whether the operation completec successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations outpu? data from the status register until another valic command is written. the status register contents arc latched on the falling edge of oe# or ce#, whichevel occurs. oe# or ce# must toggle to v,, before further reads to update the status register latch. the reac status register command functions independently o the v,, voltage. rp# can be v,, or v,,. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.l are set to ?1 ?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 7). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurre during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v,, voltage. rp# can be v,, or v,,. this command is not functional during block erase or byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. rev. 1.0
lhf08ch2 13 when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1 ?i. also, reliable block erasure can only occur when vcc=vcc2/314 and v,,=v ppi+l2/3* in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while vpp&,,,k, sr.3 and sr.5 will be set to ?1?. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp#=v,,. if block erase is attempted when the corresponding block lock-bit is set and rp#=v,,, sr.l and sr.5 will be set to ?1?. block erase operations with v,,crp#cvh, produce spurious corresponding block lock-bit be cleared or, if set, tha rp#=v,,. if byte write is attempted when the corresponding block lock-bit is set and rp#=v,, sr.1 and sr.4 will be set to ?1?. byte write operations with v,,crp#cvhh produce spurious results and should not be attempted. 4.7 block erase suspend command the block erase suspend command allows block-erase interruption to read or byte-write data ir another block of memory. once the block-erase process starts, writing the block erase suspenc command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend commanc is written. polling status register bits sr.7 and sr.e can determine when the block erase operation has been suspended (both will be set to ?1?). ry/by# will also transition to v,,. specification twhrh2 defines the block erase suspend latency. results and should not be attempted. 4.6 byte write command byte write is executed by a two-cycle command sequence. byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the -ising edge of we#). the wsm then takes over, controlling the byte write and write verify algorithms nternally. after the byte write sequence is written, the device automatically outputs status register data nhen read (see figure 6). the cpu can detect the zompletion of the byte write event by analyzing the ?y/by# pin or status register bit sr.7. at this point, a read array command can be written to read data from blocks other than that which is suspended. a byte write command sequence can also be issued during erase suspend to program data in other blocks. using the byte write suspend command (see section 4.8), a byte write operation can also be suspended. during a byte write operation with block erase suspended, status register bit sr.7 will return to ?0? and the ry/by# output will transition to v,,. however, sr.6 will remain ?1? to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to vol. after the erase resume command is written, the device automatically outputs status register data when read (see figure 7). v,, must remain at v,ph1,2,3 (the same v,, level used for block erase) while block erase is suspended. rp# must also remain at v,, or v,, (the same rp# level used for block erase). block erase cannot resume until byte write operations initiated during block erase suspend have completed. nhen byte write is complete, status register bit sr.4 should be checked. if byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for ?1 ?s that do not juccessfully write to ?0?s. the cui remains in read status register mode until it receives another :ommand. qeliable byte writes can only occur when jcc=vcc2/3,4 and vprz~vppr+t/2/3. in the absence of his high voltage, memory contents are protected against byte writes. if byte write is attempted while /+v,,,,, status register bits sr.3 and sr.4 will be ret to ?1 ?i. successful byte write requires that the rev. 1.0
lhf08ch2 14 1 4.8 byte write suspend command the byte write suspend command allows byte write interruption to read data in other flash memory locations. once the byte write process starts, writing the byte write suspend command requests that the wsm suspend the byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the byte write suspend command is written. polling status register bits sr.7 and sfi.2 can determine when the byte write operation has been suspended (both will be set to ?1?). ry/by# will also transition to voh. specification twhrhl defines the byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while byte write is suspended are read status register and byte write resume. after byte write resume command is written to the flash memory, the wsm will continue the byte write process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to v,,. after the byte write resume command is written, the device automatically outputs status register data when read (see figure 8). v,, must remain at vpph1,2,3 (the same v,, level used for byte write) while in byte write suspend mode. rp# must also remain at v,, or v,, (the same rp# level used for byte write). 4.9 set block and master lock-bit commands 4 flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates 3lock-lock bit modification. with the master lock-bit lot set, individual block lock-bits can be set using the set block lock-bit command. the set master -ock-bit command, in conjunction with rp#=v,,, jets the master lock-bit. after the master lock-bit is jet, subsequent setting of block lock-bits requires 10th the set block lock-bit command and v,, on the rp# pin. see table 6 for a summary of hardwar? and software write protection options. set block lock-bit and master lock-bit are executed b a two-cycle command sequence. the set block c master lock-bit setup along with appropriate block c device address is written followed by either the se block lock-bit confirm (and an address within thl block to be locked) or the set master lock-bit confirr (and any device address). the wsm then control the set lock-bit algorithm. after the sequence i written, the device automatically outputs statu register data when read (see figure 9). the cpu car detect the completion of the set lock-bit event b analyzing the ry/by# pin output or status register bi sr.7. when the set lock-bit operation is complete, statu: register bit sr.4 should be checked. if an error i: detected, the status register should be cleared. the cui will remain in read status register mode until : new command is issued. this two-step sequence of set-up followed b! execution ensures that lock-bits are not accidentall! set. an invalid set block or master lock-b/ command will result in status register bits sr.4 ant sr.5 being set to ?1?. also, reliable operations occu only when vcc=vcc2,3,4 and vpp=vpph,,2,3. in tht absence of this high voltage, lock-bit contents arc protected against alteration. a successful set block lock-bit operation requires tha the master lock-bit be cleared or, if the maste lock-bit is set, that rp#=v,,. if it is attempted wit1 the master lock-bit set and rp#=v,,, sr.l and sr.l will be set to ?1? and the operation will fail. set block lock-bit operations while vih lhf08ch2 15 l.10 clear block lock-bits command 411 set block lock-bits are cleared in parallel via the zlear block lock-bits command. with the master ock-bit not set, block lock-bits can be cleared using )nly the clear block lock-bits command. if the naster lock-bit is set, clearing block lock-bits requires 10th the clear block lock-bits command and v,, on he rp# pin. see table 6 for a summary of hardware md software write protection options. zlear block lock-bits operation is executed by a wo-cycle command sequence. a clear block lock-bits setup is first written. after the command is written, the device automatically outputs status register data vhen read (see figure 10). the cpu can detect :ompletion of the clear block lock-bits event by analyzing the ryiby# pin output or status register bit sr.7. yhen the operation is complete, status register bit jr.5 should be checked. if a clear block lock-bit error s detected, the status register should be cleared. ?he cui will remain in read status register mode until nother command is issued. this two-step sequence of set-up followed b\ execution ensures that block lock-bits are no accidentally cleared. an invalid clear block lock-bit: command sequence will result in status register bit: sr.4 and sr.5 being set to ?1?. also, a reliable clea block lock-bits operation can only occur wher vcc=vcc2/3,4 and vpp=vpphi12/s. if a clear bloc1 lock-bits operation is attempted while v,,rv,,,, sr.3 and sr.5 will be set to ?1?. in the absence o this high voltage, the block lock-bits content arc protected against alteration. a successful clear bloc1 lock-bits operation requires that the master lock-bit i: not set or, if the master lock-bit is set, that rp#=v,, if it is attempted with the master lock-bit set ant rp#=v,,, sr.1 and sr.5 will be set to ?1? and the operation will fail. a clear block lock-bits operatior with v,,crp#cv,, p reduce spurious results ant should not be attempted. if a clear block lock-bits operation is aborted due tc v,, or vc, transitioning out of valid range or rp# active transition, block lock-bit values are left in ar undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents tc known values. once the master lock-bit is set, ii cannot be cleared. table 6. write protection alternatives 1 master 1 block 1 operation 1 lock-bit 1 l block erase or byte write x effect block erase and byte write enabled block is locked. block erase and byte write disabled i \i 1 block lock-bit override. block erase and bvte write set block lock-bit 0 1 ?hh enabled x vi,, or vwh set block lock-bit enabled x v,h master lock-bit is set. set block lock-bit disabled vhh 1 master lock-bit override. set block lock-bit ena bled set master 1 x 1 x v,h 1 set master lock-bit disabled lock-bit clear block lock-bits 0 x 1 x v v 0rv b v \i set master lock-bit enabled clear block lock-bits enabled master lock-bit is set. clear block lock-bits disabled master lock-bit override. clear block lock-bits ?hh 1 enabled rev. 1 .o
sharp lhf08ch2 table 7. status register definition wsms / ess 1 eclbs 1 bwslbs 1 vpps 1 bwss 1 dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status check ry/by# or sr.7 to determine block erase, byte 1 = ready write, or lock-bit configuration completion. 0 = busy sr.6-0 are invalid while sr.7=?0?. sr.6 = erase suspend status if both sr.5 and sr.4 are ?1?s after a block erase or 1 = block erase suspended lock-bit configuration attempt, an improper command 0 = block erase in progress/completed sequence was entered. sr.5 = erase and clear lock-bits status sr.3 does not provide a continuous indication of v,, 1 = error in block erasure or clear lock-bits level. the wsm interrogates and indicates the v,, level 0 = successful block erase or clear lock-bits only after block erase, byte write, set block/master lock-bit, or clear block lock-bits command sequences. sr.4 = byte write and set lock-bit status sr.3 is not guaranteed to reports accurate feedback 1 = error in byte write or set master/block lock-bit 0 = successful byte write or set master/block only when v,,#v,,,,,~,,. lock-bit sr.l does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the sr.3 = v,, status master lock-bit, block lock-bit, and rp# only after block 1 = v,, low detect, operation abort erase, byte write, or lock-bit configuration command o=v,,ok sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master sr.2 = byte write suspend status lock-bit is set, and/or rp# is not v,,. reading the block 1 = byte write suspended lock and master lock configuration codes after writing 0 = byte write in progress/completed the read identifier codes command indicates master and block lock-bit status. sr.l = device protect status 1 = master lock-bit, block lock-bit and/or rp# lock sr.0 is reserved for future use and should be masked detected, operation abort out when polling the status register. 0 = unlock sr.0 = reserved for future enhancements
lhf08ch2 check if desired fullstatuscheckprocedure block erase error block erase successful command i comments / write 1 erasesetup 1 data=20h addr=wlthin block to be erased write data-doh addr=withm block to be erased read status rqster data standby check sr.7 ,=wsm ready o=wsm busy full status check can be done after each block erase or after a sequence of block erasures. wnte ffh after the last operation to place device in read array mode. bus operation command standby standby comments check sr.3 l=vpp error detect check sr. 1 l=device protect detect rp#=v,,+block lock-bit is set only required for systems implementing lock-bit configuration check sr.4,5 both t=command sequence error check sr.5 l=block erase error ;r.5,sr.4.sr.3 and sr., are only cleared by the clear status register command in casas where multiple blocks are erased before full status is checked. error is detected. clear the status register before attempting retry or other error recovery. figure 5. automated block erase flowchart rev. 1.0
shari= lhf08ch2 18 suspend byte write loop full status check procedure device protect error byte wnte successful i command comments write setup byte write datedoh addklwabon to be wlitten data=data to be written wnte byte wnte addr=lccation to be written read standby status register data check sr.7 l=wsm ready o=wsm busy repeat for subsequent byte writes. sr full status check can be done after each byte write. or after a sequence of byte writes. wnte ffh after the last byte write operation to place device iii read array mode. command comments standby check sr.3 1+,x error detect check sr. 1 standby l=devse protect detect rp#=vih,block lock-bit is set only required for systems implementing lock-btt configuration standby check sr.4 l=data wnte error 57.4.sr.3 and sr. 7 are only cleared by the clear status regtster command in cases where multiple locations are written before full status is checked. f error is detected, clear the status register before attempting retry or other error reco?ely. figure 6. automated byte write flowchart rev. 1 .o
lhf08ch2 start write boh status register bus operation command i comments i check 533.7 1 =wsm reacty o=wsm busy check sr.6 l=block erase suspended o=block erase completed write el-&% data=doh resume addr=x figure 7. block erase suspend/resume flowchart rev. 1.0
lhf08ch2 r i:t sr.7= 0 1 bus operation command i write byte write suspend data=boh addr=x read status regster data addr=x standby check sr.7 1 =wsm ready o=wsm busy standby check sr.2 l=byte write suspended o=byte write completed read army data=ffh addr=x figure 8. byte write suspend/resume flowchart rev. 1.0
sharp lhf08ch2 21 write oihifih, check if desired full status check procedure read status register data(see above) device protect error set lock-bit error set lock-bit successful bus operation command commenb write write set block/master lock-bit sehrp set block or master lock-bit confirm data=6oh addr=block address(block), dewca address(master) data=olh(block), flh(master) addr=blcck address(block), device address(master) read status register data standby check sr.7 l=wsm ready o=wsm busy repeat for subsequent lock-bit set operations. full status check can be done after each lock-btt set oper?dtion or after a sequence of lock-bit set operations. wnte ffh after the last lock-bit set operation to place device i? read army mode. bus operation command comment3 standby check sr.3 t=vpp error detect check sr.1 i=dewce protect detect standby rp#+, (set master lock-blt operation) rp#=vih, master lock-bit is set (set block lock-blt operation) standby check sr.4,5 both l=command sequence error standby check sr.4 l=set lock-bit error sr.5.sr.4,sr.3 and sr.1 are only cleared by the clear status register command i? cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 9. set block and master lock-bit flowchart rev. 1.0
lhf08ch2 22 start x write 60h + 0 sr.7= 1 check if desired full status check procedure device protect error \ nrite ffh after the clear block lock-bits operation to f hate device in read array mode. bus operation command comments wi-its write clear block lock-bits setup clear block lock-bits confirm data=m)h addr=x data=doh addr=x read status register data standby check sa.7 l=wsm ready o=wsm busy bus operation command comments standby check sr.3 l=vpp error detect standby check sr. 1 mjevice pmtect detect rp#=v,h, master lock-bit is set standby check sr.4,5 both l=command sequence error standby check sr.5 l&tear block lock-bits error sr.5.sr.4.sr.3 and sr. 1 are only cleared by the clear status register command. f error is detected, clear the status register before attempting retry or other error recovery. figure 10. clear block lock-bits flowchart rev. 1.0
lhfosch2 23 1 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# and block erase, byte write, and lock-bit configuration polling ry/by# is a full cmos output that provides a lardware method of detecting block erase, byte write snd lock-bit configuration completion. it transitions ow after block erase, byte write, or lock-bit :onfiguration commands and returns to v,, when he wsm has finished executing the internal algorithm. 3y/by# can be connected to an interrupt input of the ;ystf?m cpu or controller. it is active at all times. ry/by# is also voh when the device is in block eras suspend (with byte write inactive), byte write suspenc or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers arc interested in three supply current issues; standb current levels, active current levels and transien peaks produced by falling and rising edges of cei and oe#. transient current magnitudes depend oi the device outputs? capacitive and inductive loading two-line control and proper decoupling capacito selection will suppress transient voltage peaks. eacl device should have a 0.1 uf ceramic capacito connected between its voo and gnd and between it: v,, and gnd. these high-frequency, low inductance capacitors should be placed as close as possible tc package leads. additionally, for every eight devices a 4.7 uf electrolytic capacitor should be placed at the array?s power supply connection between v,, ant gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vpp trace on printed circuit boards updating flash memories that reside in the targe system requires that the printed circuit boarc designer pay attention to the v,, power supply trace the v,, pin supplies the memory cell current for by& writing and block erasing. use similar trace width: and layout considerations given to the voc powel bus. adequate v,, supply traces and decoupling wil decrease v,, voltage spikes and overshoots. rev. 1.0
lhf08ch2 24 1 5.5 vcc, vpp, rp# transitions block erase, byte write and lock-bit configuration are not guaranteed if v,n falls outside of a valid v,,,,,,, range, vcc falls outside of a valid vcc2,3,4 range, or rp#&,,, or v,,. if v,, error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v,, during block erase, byte write, or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v,, clear the status register. the cui latches commands issued by system software and is not altered by v,, or ce# transitions or wsm actions. its state is read array mode upon sower-up, after exit from deep power-down or after vcc transitions below vlko. after block erase, byte write, or lock-bit configuration, 3ven after v,, transitions down to vpplk, the cui nust be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against 3ccidental block erasure, byte writing, or lock-bit :onfiguration during power transitions. upon lower-up, the device is indifferent as to which power supply (v,, or vcc) powers-up first. internal circuitr resets the cui to read array mode at power-up. a system designer must guard against spuriou: writes for vcc voltages above vlko when v,, i! active. since both we# and ce# must be low for i command write, driving either to vi, will inhibit writes the cul?s two-step command sequence architecturt provides added level of protection against datr alteration. in-system block lock and unlock capability prevent: inadvertent data alteration. the device is disablec while rp#=v,, regardless of its control inputs state. ? 5.7 power dissipation when designing portable systems, designers mus consider battery power consumption not only durin! device operation, but also for data retention during system idle time. flash memory?s nonvolatilih increases usable battery life because data is retainec when system power is removed. in addition, deep power-down mode ensure: extremely low power consumption even when systen power is applied. for example, portable computing products and other power sensitive applications tha use an array of devices for solid-state storage car consume negligible power by lowering rp# to vi, standby or sleep modes. if access is again needed the devices can be read following the tphav ant tphwl wake-up cycles required after rp# is firs raised to v,,. see ac characteristics- read only and write operations and figures 15, 16 and 17 fol more information. rev. 1.0
lhf08ch2 25 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase, byte write and lock-bit configuration . . . . . . . . . ..o?c to +7o?c(1) temperature under bias . . . . . . . . . . . . . . . -10c to +8o?c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125?c voltage on any pin (except vcc, vp,, and rp#) . . .._.. -2.ov to +7.ov@) v,, supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -2.ov to +7.0@) v,, update voltage during block erase, byte write and lock-bit configuration . . . . . . . . . . . -2.ov to +14.ov(2j) rp# voltage with respect to gnd during lock-bit configuration operations . . . . . . -2.ov to +14.0v(2j) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . 1 00mac4) *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions ? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notes: 1. operating temperature is for commercial temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v,, and v,, pins. during transitions, this level may undershoot to -2.ov for periods <20ns. maximum dc voltage on input/output pins and voc is vcc+o.si which, during transitions, may overshoot to vcc+2.ov for periods c20ns. 3. maximum dc voltage on v,, and rp# may overshoot to +14.ov for periods <20ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and vcc operating conditions symbol 1 parameter 1 notes min. 1 max. 1 unit 1 test condition t, ( operating temperature 0 1 +70 i ?c i ambient temperature van, vcc supply voltage (2.7v-3.6v) 1 2.7 3.6 v vr-c, vnn supply voltage (3.3v+o.3v) 3.0 3.6 v voo2 vnr. supply voltage (5v+o.25v) 4.75 5.25 v v,, vnn supply voltage (5v+o5v) 4.50 5.50 v note: 1. block erase, byte write and lock-bit configuration operations with vo,<3.ov should not be attempted. 6.2.1 capacitance(?) symbol parameter c,n input capacitance ca,t output capacitance note: 1. sampled, not 100% tested. t,=+25?c, f=l mhz typ. max. 6 8 8 12 unit condition pf v,,=o.ov pf v(-y ,j-=o.ov rev. 1.11
lhf08ch2 1.2.2 ac input/output test conditions 1:; -t--,j(z2~+--y ac test inputs are driven at 2.7v for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (10% to 90%) lhf08ch2 27 l2.3 dc characteristics dc ch vcc=2.7v typ. 1 max. i racteristics al - uni ija cia vcc=vccmax. ce#=rp#=v,,., rp#=gnd*0.2v b, ,,(ry/by#)=oma cmos inputs vcc=vccmax. ce#=gnd f=5mhz(3.3v, 2.7v), 8mhz(5v) in, ,t=oma ttl inputs v,,=v,,max. ce#=gnd f=5mhz(3.3v, 2.7v), 8mhz(5v) vcr lre, 20 0.2 parameter votes input load current 1 output leakage current 1 v,, standby current 1,3,6 vcc deep power-down current dcc read current 1 133 ticc byte write or set lock-bit current dcc block erase or zlear block lock-bits zurrent i,, byte write or block irase suspend current ipp standby or read hrrent i,, deep power-down hrrent fpp byte write or set .ock-bit current ~ i,7 1,7 v--- sym. ?li ko.5 * ko.5 20 100 ?lo =lx 100 25 100 ?cc, ija 0.1 2 ma pa ma i ccd ccr l-l- 12 17 35 7 7 18 8 18 20 50 ma in, ,t=oma vdo=3.3v*o.3v - - - - - - s - - - - - - i i 17 i - i - ma ma ma ma ma ma ccw cce 6 1 1 1 10 ma ce#=v,,, 1 :cws lxxs. ?ps tel...- ?pd ?pw - - _+2 *15 10 200 0.1 5 - - - - - - - -? - - - - & cia ija ma ma ma ma ma ma vpp_vcc. a2 10 0.1 rp#=gnd*0.2v vpp=3.3v~0.3v dpp=5.0v+0.5v vpp=12.0v+0.6v vpp=3.3v~o.3v vpp=5.0v+o.5v vp,=1 2.ov&o.6v 40 - - 40 40 15 15 _ 20 - - 20 20 15 15 200 10 200 ipp block erase or zlear lock-bit current ?pe ?pws ipp byte write or block 9xs- :rase suspend current 10 rev. 1.2
sharp lhfobch2 28 sym. parameter notes v,, input low voltage 7 4, input high voltage 7 vol output low voltage 3,7 i vohl output high voltage v-j 3,7 voh2 output high voltage (cmos) 3,7 lock-bit operations v,,r+ v,, during byte write, block erase or lock-bit operations v,,hs v,, during byte write, block erase or lock-bit operations v, kr, vcr: lockout voltage vhh f?p# unlock voltage 8,9 iotes: dcc &-.& min. -0.5 2.0 2.4 0.85 yc.cl vcc -0.4 - - - 2.0 - :h ,aracteristics continued =; !.7v vcc=3.3v 1 vc.,dv max. min. max. min. 0.8 -0.5 0.8 -0.5 vcc +0.5 2.0 vcc +0.5 2.0 i i i 1 0.85 1 0.85 - j 11.4 / 12.6 / 11.4 12.6 max. 0.8 vcc +0.5 0.45 1.5 - 5.5 12.6 unit v v v v v v v v v v v v test conditions vcc=vccmin. ,=5.8ma(vcc=5v), io lol=2.0ma (vnn=3.3v, 2.7v) vcc=vcomin. loh=-2.%la(vcc=5v), lo,=-2.0ma(vcc=3.3v) in,,=-1 .5ma(vr.,=2.7v) in!+=-1 ooua set master lock-bit override master and block lock-bit . all currents are in rms unless otherwise noted. typical values at nominal voc voltage and t,=+25?c. these currents are valid for all product versions (packages and speeds). . ?ccws and ?cces are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of lccws or ioces and lccr or i,,,, respectively. ?. includes ry/by#. . block erases, byte writes, and lock-bit configurations are inhibited when v&j,,,,, and not guaranteed in the range between vpplk(max.) and vppht(min.), between vnr+n(max.) and vpp&min.), between vpp&max.) and vpphs(min.), and above vpphs(max.). . automatic power savings (aps) reduces typical i,,, to 1 ma at 5v vcc and 3ma at 2.7v and 3.3v voc in static operation. . cmos inputs are either vco- +0.2v or gndk0.2v. ttl inputs are either v,, or vi,. . sampled, not 100% tested. . master lock-bit set operations are inhibited when rp#=v,,. block lock-bit configuration operations are inhibited when the master lock-bit is set and rp#=vrh. block erases and byte writes are inhibited when the corresponding block-lock bit is set and rp#=vrh. block erase, byte write, and lock-bit configuration operations are not guaranteed with vcc <3.ov or vrh lhfosch2 29 6.2.4 ac characteristics - read-only operations(?) i vc,,=2.7v-3.6v, t,po?c to +7o?c versiond4) lh28f008sgl150 1 sym. 1 parameter .-- 1 notes 1 min. max. 1 unit 11 tr,, nx oe# to outr ghc)7 lh oe# high to output in high z output hold from address, ce# ot whichever occurs first 3 0 ns note: see 5.ov v,, read-only operations for notes 1 through 4. -0c to +7o?c . ..------sc-l,20 max. unit vc:,=3.3v+0.3v, tg versiond4) lh28fo08 sym. parameter 1 notes min. tj?a? read cyc& time 120 ns ta?n? addre: ns tf, (-jv tpwnv 1 rp# hiqh to output delay t note: see 5.ov v,, read-only operations for notes 1 through 4. rev. 1.0
si-iarp lhf08ch2 30 vcc=5vdl.5v, 5vko.25v, t,=o?c to +70x vcc=5v+0.25vj lh28fo08sc-l=(5) 1 i sym. t*?n? read cycle t*?n? address to c ce# to outp tphn? rp# high to oe# to outp ce# to outp ce# high to vuhc/ul ,,, k, nx oe#to output in low z output hold from address, change, whichever occurs notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to telqv-tglqv after the falling edge of ce# without impact on telqv. 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high speed configuration) for testing characteristics. 6. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. rev. 1.11
sharp lhf08ch2 31 l device address selection data valid t .i.,....,, address stable r vih ce#(e) vil c vih oe#(g) wl vih we#(w) vil toh,--+ voh ,1,,,,,,,, data(d/q) (dqo-dq7) vol vcc vih rp#(p) vil figure 15. ac waveform for read operations rev. 1.0
sharp lhf08ch2 32 6.2.5 ac characteristics - write opera - ation vc.=2.7v-3.6v, ta=o?c to +7o?c versiond5) lh28f008sgl150 parameter notes min. 1 max. unit ta?a? write cycle time 150 ns tpl-!wl rp# high recovery to we# going low 2 1 ijs note: see 5.ov v,, we#-controlled writes for notes 1 through 5. svm. i vcc=3.3v+0.3v, t?,=o?c to +70x versiond5) parameter 1 notes 1 lh28f008sc-l120 min. max. unit --..- t d\,a\l 1 write cvcle time 120 ns i we# going low we# going low ulse width 2 1 p3 0 ns 70 ?c & 1 rp# vhh setup tvpwcl 1 vpp setup to we tpuw, rp# high recovery tc ff, w, ce# setup to twl wh we#p- -- ~~ i._ to we# going high 2 100 ns !# going high 2 100 ns t*,,-,,,,,, [ address setup to we tnvw,, [ data setup to we# g # going high oing high i we# high from we# hiah 3 50 ns 3 50 ns 5 ns 5 nc twwnx 1 data hold fron twhax ) address hold i *u ve# high 0 ns i high 25 ns by# going low 100 ns twhfh ce# hold from v bachw, we# pulse width twhr, we# high to ry/ bur,, write recovery before read 0 ns tn?v, vpp hold from valid srd, ry/by# high 2,4 0 ns tn?ph rp# v,,,, hold from valid srd, ry/by# high 2,4 0 ns iote: ;ee 5v v,, ac characteristics - write operations for notes 1 through 5. rev. 1.2
lhfosch2 uotes: i. read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-onry operations. refer to ac characteristics for read-only operations. !. sampled, not 100% tested. 3. refer to table 4 for valid a,, and d,, for block erase, byte write, or lock-bit configuration. 1. v,, should be held at vpph1,2,3 ( and if necessary rp# should be held at v,,) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high seed configuration) for testing characteristics. 7. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. rev. 1.2
sharp lhfobch2 addresses(a) ce#(e) oe#(g) we#(w) data( d/q) ry/by#(r) rp#(p) 1 2 3 4 5 6 rcs----- vih vih vil vih vil vih voh twhgl notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 16. ac waveform for we#-controlled write operations rev. 1 .o
lhf08ch2 35 6.2.6 alternative ce#-controlled writes(?) vc:,=2.7v-3.6v, t,=o?c to +7o?c versiond5) parameter 1 notes 2 lh28f008sgl150 min. max. 150 1 0 70 unit 3 50 3 50 5 ee 5 0 25 f-l i ? see 5.ov v,, alternative ce#-controlled writes for notes 1 through 5. ns ns vbc=3.3v+0.3v, t,=o?c to +70x versiond5) i lh28f008sc-l120 parameater min. max. unit sym. . .a.-...---. t*?n? write cycle time tp&p, rp# high recovery to ce# tw, f, we# setup to ce# p-?-- ? tp, fh ce# pulse width t rp# v,, setup to ccw .-- : going low 2 1 p.s uullly low 0 ns -7n t i nc i i.2 3 i---c-- ns tfq&, ce# pulse width high tp)+q ce# high to ry/by# going low ffzhr,, write recovery before read hnl vpp hold from valid srd, ry/by# high 2,4 w?ovph rp# vhh hold from valid srd, ry/by# high 2,4 note: see 5v vc, alternative ce#-controlled writes for notes 1 through 5. 25 ns 100 ns 0 ns 0 ns 0 ns rev. 1.0
lhf08ch2 etuo to cl 7? 7? ii> ii> 40 40 ns ns 5 5 ns ns -! -! 5 5 ns ns 0 0 ns ns 9r; 9r; -a -a notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and din for block erase, byte write, or lock-bit config.uration. 4. v,, should be held at vpphl12,s ( and if necessary rp# should be held at v,,) until determination of block erase byte write, or lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). 6. see transient input/output reference waveform and transient equivalent testing load circuit (high seed configuration) for testing characteristics. 7. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. rev. 1 .ll
addresses(a) we#(w) oe#(g) ce#(e) data( d/q) ry/by#(r) rp#(p) vil voh vol j vhh vih vil - 1 2 3 4 5 a---- a vih vil vih vil vih vil vih notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. lhf08ch2 37 figure 17. ac waveform for ce#-controlled write operations rev. 1.0
sharp lhf08ch2 2.7 reset operations voh ry/by#(r) vol vih flp#(p) vil (a)reset during read array mode voh ry/by#(r) vol p tplah vih rp#(p) vil (b)reset during block erase, byte write, or lock-bit configuretion 2.7vi3.3vi5v l vcc ml - b35vph - vih rp#(p) i vil 7- (c)rp# rising timing figure 18. ac waveform for reset operation reset ac specifications(?) vr.,=2.7v vn,=3.3v v~+iv sym. parameter notes min. max. min. max. min. max. unit rp# pulse low time ?lph (if rp# is tied to vcc, this 100 100 100 ns specification is not applicable) rp# low to reset during ?lrh block erase, byte write or 2,3 - 20 12 p lock-bit configuration v,, 2.7v to rp# high 35vph v,, 3.ov to rp# high 4 100 100 100 ns vco 4.5v to rp# high ites: these specifications are valid for all product versions (packages and speeds). if rp# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 1 oons. a reset time, tphqv, is required from the latter of ry/by# or rp# going high until outputs are valid. when the device power-up, holding rp# low minimum 1oons is required after vcc has been in predefined range and also has been in stable there. rev. 1.0
lhf08ch2 6.2.8 block erase, byte write and lock-bit configuration performance(3~4~5) :whqv4 clear block lock-bits time 2 1.1 5 1 4 s fhova twhrh, byte write suspend latency time to read 5.6 7 5.2 7.5 tf,,rh, p )?hnhz erase suspend latency time to read 9.4 13.1 9.8 12.6 ijs fhrh7 notes: 1. typical values measured at ta=+25?c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. block erase, byte write and lock-bit configuration operations with vccc3.ov and/or vpp<3.0v are not guaranteed. rev. 1.3
sharp lhf08ch2 additional information 1 ordering information product line designator for all sharp flash products i i i ~l~h12/81f~o~018/sici(h~rl- lll815j w device density access speed (ns) 008 = 8-mbit f 85:85ns(5v,30pf), 90ns(5v), architecture 120ns(3.3v), 150ns(2.7v) s = regular block 12:120ns(5v), 150ns(3.3v) 170ns(2.7v) power supply type ~ c = smartvoltage technology ul pat kage t = 40-lead tsop operating temperature r = 40-lead tsop(reverse bend) ?blank = 0c - +7o?c - n = 44-lead psop h = -40c - +85?c b = 42 or 48-ball csp _ valid operational combinations v,,=2.7-3.6v v,,=3.3*0.3v vc+.o*o.5v vcc=5.0~0.25v 5opf load, 5opf load, 1 oopf load, 3opf load, )ption order code 1.35v i/o levels 1.5v i/o levels ttl l/o levels 1.5v i/o levels 1 lh28foo8scfbl85 lh28f008sc-l150 lh28f008sc-l120 lh28f008sc-l90 lh28f008sc-l85 rev. 1.0
sharp lhf08ch2 8 package and packing specification 1 - 1 1. package outline specification refer to drawing no.aa 1 1 12 2. markings 2 - 1. marking contents ( 1) product name : LH28F008SCR-L85 ( 2 ) company name : sharp (3) date code (example) y y ww xxx indicates the product was manufactured (lower two digits of the year.) 2 - 2. marking layout refer drawing no.aal 1 1 2 (this layout does not define the dimensions of marking character 3. pack ing specification (dry packing for surface mount packages) ( (4) the marking of ?japan? indicates the country of origin. and mark ing position.) dry packing is used for the purpose of maintaining ic quality after mounting packages on the pcb (printed circuit board), when the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. if the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip,lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. vps). this causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. this dry packing is designed to prevent the above problem from occurring in surface mount packages. - 1. packing materials material name material specificaiton purpose tray conductive plastic (50devices/tray) fixing of device _____________.__________________________--~-----~~---~~~----~------~-~----~~-----~~~~-~-----~~~~---~~~~--..----~.----~------.---------------------- _ _ _ _ _ _ _ _ upper cover tray conductive plast ic (ltray/case) fixing of device ________________________________________---------.---------------------------------------------------- ___--____-____-_________________________---- _ _ _ _ _ _ _. _. laminated aluminum bag aluminum polyethylene (lbag/case) drying of device ________________________________________-------------------------------------------------------------------------------------------------------------------. desiccant silica gel drying of device ._______________________________________~~~~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __._____________________________________---.---------. p p band polypropylene (3pcs/case) fixing of tray ________________________________________~~-~~~~---~~~---~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~~~.~~~~~~~~.~~~~~.~~~~~~~~~~~~~~~~~~~~~~~--~~~~~~~~~~~-~~~~~~~~~~~~~~ inner case card board (500devices/case) packaging of device ________________________________________~~.--~~..--~~~--~~~~~---~~~~.--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~-~~~~~~-~~~~~--~~~~-~~~~~~~~~~.~-~~~~~~~~. label paper indicates part number,quantit] and date of manufacture ,____________.______~~~~~..~~~~..~~~~~~.~~~~~~~~~~.~.~~~~~~.~~~~~~.~~~~~~~.~~~~~~~~~~.~.~~~~~~...~~~~...~~~~~.~.~~~~.~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~. outer case card board cuter packing of tray devices shall be placed into a tray in the same direction.)
sharp lhf08ch2 42 3 - 2. outline dimension of tray refer to attached drawing 4. storage and opening of dry packing 4-l. store under conditions shown below before opening the dry packing ( 1) temperature range : 5-40c (2) humidity : 80% rh or less 4 - 2. notes on opening the dry packing (1) before opening the dry packing, prepare a working table grounded against esd and use a grounding strap. (2) the tray has been treated to be conductive or anti-stat i device is transferred to another tray, use a equivalent 4-3. storage after opening the dry packing perform the following to prevent absorption of moisture after which is c. if the tray. opening. (1) after opening the dry packing, store the ics in an environment with a temperature of 5-25c and a relative humidity of 60% or less and mount ics within 72 hours after opening dry packing. 4 -4. baking (drying) before mounting ( 1) baking is necessary (a) if the humidity indicator in the desiccant becomes pink (b) if the procedure in section 4-3 could not be performed ( 2) recommended baking conditions if the above conditions (a) and (b) are applicable, bake it before mounting, the recommended conditions are 16-24 hours at 120c. heat resistance tray is used for shipping tray. 5. surface mount conditions please perform the following conditions when mounting ics not to deteriorate ic quality. 5-l .soldering conditions(tbe following conditions are valid only for one time soldering.) mounting method temperature and duration measurement point reflow soldering peak temperature of 230c or less, ic package (air) duration of less than 15 seconds. surface 200c or over,duration of less than 40 seconds. temperature increase rate of l--4?vsecond _______.__________._____________________-------------------.-------------------------------------------------------. ___________________._____________ manual soldering 260c or less, duration of less ic outer lead (soldering iron) than 10 seconds. surface 5 - 2. cond (1) (2) (3) itions for removal of residua 1 ultrasonic washing power washing time solvent temperature flux : 25 watts/liter or less : total 1 minute maximum : 15-40c
sharp lhf08ch2 0 . h) \r. ul it l h28f008scr- japan yyww xx l8 x 5 20. 0+-o. 3 18. 4&o. 2 t- ase plane see detail a detail a ;i% j !j-fttjz [ tin-leac ikii* ?1s~f~9);~b-'im~~,t18~~ll~\bq)lff3. 4me $sop40-p-lozo(r lead finish j plating note plastic body dimensions do not include burr #{z j of resin. mawing no. i aa1112 unit ! mm
sharp lhf08ch2 44 mq tlw qame\tsop40-1020tcm-rh note qqil j drawing no. j cv644 unit 1 mm
sharf, lhf708ch2 45 flash memory lhfxxcxx family data protection ificat on may be noises having a level exceeding the limit specified in the spec generated under specific operating conditions on some systems. such noises, when induced onto west signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block when a lock bit is set, the corresponding block is protected against overwriting. by using this feature, the flash memory space can be divided into the program section(locked section) and data section(unlocked section). the master lock bit can be used to prevent false block bit setting. by controlling ri%, desired blocks can be locked/unlocked through the software. for further information on setting/resetting block bit and control to the specification. (see chapter 4.9 and 4.10) 2) data protection through vpp ing of rp#, refer when the level of vpp is lower than vpplk (lockout voltage), write operation on the flashmemory is disabled. all blocks are lockedandthedata intheblocksarecompletely write protected. for the lockout voltage, refer to the specification. (see chapter 6.2.3. ) 3) data protect ion through rp# when the rp$ is kept low during power up and power down sequence such as vo 1 tage transition, write operation on the flash memory is disabled, write protecting all blocks. for the detai 1s of rpb control, refer to the specification. (see chapter 5.6 and6.2.7.) rev 1.3

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